/*
 * Copyright (c) 2022-2023 Termony Co., Ltd. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice, this list of
 *    conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
 *    of conditions and the following disclaimer in the documentation and/or other materials
 *    provided with the distribution.
 *
 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
 *    to endorse or promote products derived from this software without specific prior written
 *    permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _LOS_ARCH_CPU_H
#define _LOS_ARCH_CPU_H

#include "los_config.h"
#include "los_compiler.h"

#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */

#define __REG32(x)          (*((volatile UINT32 *)(x)))
#define __REG64(x)          (*((volatile UINT64 *)(x)))

#define __WFI()             __asm__ __volatile__("wfi" ::: "memory")
#define __ISB()             __asm__ __volatile__("isb sy" ::: "memory")
#define __DSB()             __asm__ __volatile__("dsb sy" ::: "memory")
#define __DMB()             __asm__ __volatile__("dmb sy" ::: "memory")

#define GET_ARM_SYS_REG(reg, out) \
                __asm__ __volatile__("mrs %0, " reg : "=r"(out) :: "memory")
#define SET_ARM_SYS_REG(reg, in)  \
                __asm__ __volatile__("msr " reg ", %0" :: "r"(in) : "memory")


#define MPIDR_EL1           "MPIDR_EL1"

/* AArch64 System register interface to GICv3. */
#define ICC_IAR0_EL1        "S3_0_C12_C8_0"
#define ICC_IAR1_EL1        "S3_0_C12_C12_0"
#define ICC_EOIR0_EL1       "S3_0_C12_C8_1"
#define ICC_EOIR1_EL1       "S3_0_C12_C12_1"
#define ICC_HPPIR0_EL1      "S3_0_C12_C8_2"
#define ICC_HPPIR1_EL1      "S3_0_C12_C12_2"
#define ICC_BPR0_EL1        "S3_0_C12_C8_3"
#define ICC_BPR1_EL1        "S3_0_C12_C12_3"
#define ICC_DIR_EL1         "S3_0_C12_C11_1"
#define ICC_PMR_EL1         "S3_0_C4_C6_0"
#define ICC_RPR_EL1         "S3_0_C12_C11_3"
#define ICC_CTLR_EL1        "S3_0_C12_C12_4"
#define ICC_CTLR_EL3        "S3_6_C12_C12_4"
#define ICC_SRE_EL1         "S3_0_C12_C12_5"
#define ICC_SRE_EL2         "S3_4_C12_C9_5"
#define ICC_SRE_EL3         "S3_6_C12_C12_5"
#define ICC_IGRPEN0_EL1     "S3_0_C12_C12_6"
#define ICC_IGRPEN1_EL1     "S3_0_C12_C12_7"
#define ICC_IGRPEN1_EL3     "S3_6_C12_C12_7"
#define ICC_SGI0R_EL1       "S3_0_C12_C11_7"
#define ICC_SGI1R_EL1       "S3_0_C12_C11_5"
#define ICC_ASGI1R_EL1      "S3_0_C12_C11_6"

/* AArch64 System register interface to General Timer. */
#define CNTFRQ_EL0          "CNTFRQ_EL0"
#define CNTPCT_EL0          "CNTPCT_EL0"
#define CNTP_CTL_EL0        "CNTP_CTL_EL0"
#define CNTP_TVAL_EL0       "CNTP_TVAL_EL0"
#define CNTP_CVAL_EL0       "CNTP_CVAL_EL0"


UINT32 HalGetCpuId(VOID);
UINT32 HalGetAffinity(VOID);
UINT32 HalGetAffinityFromCpuId(UINT32 cpuId);

#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */

#endif /* _LOS_ARCH_CPU_H */